Semiconductor devices such as stand alone memories, microprocessors, or microcontrollers typically have a memory array within those devices. In many instances the memory array includes a plurality of static random access memory (SRAM) memory cells. One common design for an SRAM cell is illustrated in FIG. 1. The SRAM cell 10 includes a pair of pass transistors 11 and 12 that are connected to a bit line (BL) and a complementary bit line (BL*). The other portion of transistor 11 is connected to the drains of N-type latch transistor 13 and P-type load transistor 15. The other portion of pass transistor 12 is connected to the drains of N-channel latch transistor 14 and P-channel load transistor 16. As seen in FIG. 1, the gate electrodes of latch transistor 13 and the load transistor 15 are connected to the drains of transistors 14 and 16. Likewise, the gate electrodes of transistors 14 and 16 are connected to the drains of transistors 13 and 15. The sources of transistors 13 and 14 are connected to a V.sub.SS electrode, and the sources of the transistor 15 and 16 are connected to a V.sub.DD electrode. The gate electrodes for the pass transistors 11 and 12 are part of a word line and are electrically connected to each other. In a semiconductor device, typically the circuitry outside of the memory array includes CMOS logic and sense amplifiers, column decoders, row decoders, buffers, as well as other circuitry.
In a stand alone SRAM memory device, typically all of the gate electrodes are formed using an N+ silicon layer. In this device all of the N-channel transistors will be surface channel transistors and all P-channel transistors will be buried channel transistors. The formation of buried channel transistors typically causes the threshold voltage of such transistors to be higher. The higher operating potential of the P-channel transistors within the peripheral portion typically accrues a time delay for accessing data within the memory and is generally not desired. In microcontroller and microprocessor applications, typically the N+ gates are formed over N-channel transistors and P+ gates are formed over P-channel transistors. Such a layout is generally not preferred in portions of the device that have very tight dimensions, particularly, the memory array portion, as the alignment of the N+ and P+ doping of the same polysilicon layer is difficult to do given small misalignment tolerances.